The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a vertical transistor having a bottom source/drain structure including a doped semiconductor buffer layer and an epitaxial doped semiconductor layer.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar (or fin) defines the channel with the source and drain located at opposing ends of the semiconductor pillar. Vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
In conventional vertical transistor fabrication, the forming of the bottom source/drain and subsequent source/drain extension and source/drain junction are very challenging due to integration and thermal budget restrictions. There is thus a need for providing vertical transistors in which the formation of the bottom source/drain, the source/drain extension and the junction can be easily integrated into a vertical transistor processing flow, without negatively impacting any thermal budget restrictions.